A known MOSFET 10 is shown schematically in FIG. 1. A MOSFET 10 is typically fabricated on a semiconductor substrate 12 such as silicon and has a source region 15 (also known as a ‘deep’ source region) and a drain region 16 (also known as a ‘deep’ drain region) separated by a conduction channel 17.
A gate stack 18 is provided over the conduction channel 17 (hereinafter referred to as the ‘channel’). The gate stack 18 is formed from a gate dielectric layer 19 above the channel 17, and a gate electrode 20 above the gate dielectric layer 19. The application of a potential to the gate electrode 20 allows a flow of current along a length of the channel 17 between the source 15 and the drain 16 to be controlled.
The gate stack 18 is provided with spacer elements 21, 22 on a source side and a drain side, respectively, of the gate stack 18. The purpose of the spacer elements 21, 22 is to define boundaries of the source and drain regions 15, 16 with respect to the channel 17. For example, the source and drain regions 15, 16 may be made by implantation of the substrate 12 with dopant.
The spacer elements 21, 22 may serve as an implantation mask during formation of the source and drain regions 15, 16 to define the boundary between the source and drain regions 15, 16 and the channel 17. Alternatively, the source and drain regions 15, 16 may be made by etching a source recess and a drain recess, and filling the recesses with in-situ doped silicon. In this case, the spacer elements 21, 22 serve to protect the underlying substrate from the effects of the etching process.
MOSFET devices may be formed having a channel region of either n-type doped semiconductor material (NFET device) or p-type doped semiconductor material (PFET device). A recent advance in the development of higher performance MOSFET devices has been the inclusion of strained silicon regions in the devices. It has been found that the drive current of an NFET may be enhanced by applying a tensile stress along the length of the channel 17. The performance of a p-type FET (PFET) may be enhanced by applying a compressive stress along the length of the channel 17 instead of a tensile stress.
However, if a compressive stress is applied along the length of the channel 17 of an NFET the performance of the NFET is degraded. Similarly, if a tensile stress is applied along the length of the channel 17 of a PFET, the performance of the PFET is degraded.
It is known that layers of material can be formed having either a tensile stress or a compressive stress, depending upon the conditions under which the layer is formed. By conditions is included parameters such as growth temperature, deposition rate, layer composition, etc. For example, silicon nitride layers may be formed having a compressive stress or tensile stress depending upon the conditions under which the silicon nitride layer is formed. The layer may induce a corresponding compressive or tensile stress in the structure underlying the layer.
The performance of PFET devices can thereby be enhanced by forming a compressive stressed silicon nitride layer over the PFET devices. The performance of NFET devices can be enhanced by forming a corresponding tensile stressed silicon nitride layer over the NFET devices.
FIG. 2 shows a pair of MOSFET devices 100 formed on a semiconductor substrate. The devices 100 have gate stacks 118, and sidewall spacers 121, 122 provided on sidewalls of the gate stacks 118. A stress liner layer 125 is provided over the MOSFET devices 100. The stress liner layer 125 is formed to have either a compressive stress or a tensile stress. A stress liner layer 125 having a compressive stress is formed over PFET devices, whilst a stress liner layer 125 having an internal tensile stress is formed over NFET devices.
MOSFET devices may be formed to have a nested configuration, or an isolated configuration. In a nested configuration, adjacent MOSFET devices are formed in close proximity to one another such that a single volume of doped semiconductor material forms the source region of one MOSFET device and the drain region of an adjacent MOSFET device. The devices thus ‘share’ a volume of doped semiconductor material. Nested devices may be formed such that a single silicide contact to the volume of doped semiconductor material serves as a source contact to one MOSFET device and as a drain contact to the adjacent MOSFET device.
In an isolated configuration, MOSFET devices are formed each having a single polycrystalline silicon gate region. In a nested configuration, a plurality of devices are provided, some of the polycrystalline silicon gate regions of the devices being connected to one another.
It is known that a performance difference exists between NFET and PFET devices. PFET devices generally have a performance that is inferior to that of NFET devices. This is at least partly due to the fact that in PFET devices holes are responsible for current conduction in the channel region of the device, whilst in NFET devices electrons are responsible for current conduction in the channel region.
However, it is also found that a difference in performance exists between PFET devices in a nested configuration when compared with PFET devices in an isolated configuration. PFET devices in a nested configuration are generally found to have inferior performance compared with PFET devices in an isolated configuration. This is at least partially due to the fact that as the PC to PC distance is reduced, the amount of stress liner layer present between adjacent PCs is reduced. A significant decrease in the amount of stress imparted to the substrate by the stress liner layer is observed as the PC to PC distance is reduced.
By ‘performance’ is meant a characteristic of the device such as an on-state drain current (Ion), a saturation drain current (Idsat) or a maximum transconductance (Gmax). By performance ‘difference’ between isolated and nested devices is meant that the value of a performance characteristic of a given nested MOSFET device is different from the corresponding value of a given isolated MOSFET device.